1. Field of the Invention
The present invention relates to an ECL test circuit for easily testing an ECL circuit.
2. Description of the Prior Art
FIG. 8 shows a conventional integrated circuit (IC) 100 having ECL circuits, E3 to En. The IC 100 includes NPN transistors Q3 to Qn for supplying bias currents, I3 to In, to the ECL circuits E3 to En, respectively, while NPN transistors, Q1 and Q2, control values of the bias currents I3 to In. The transistor Q1 has a collector where constant current IO from a constant current circuit 4 flows. The transistors, Q1 to Qn, together with resistors, R2 to Rn, organize a current mirror circuit, where there are relations expressed as follows: EQU IO=I3=. . . =In (1)
FIG. 9 is a circuit diagram showing an inner structure of the IC 100, where merely an ECL circuit E3 and the next stage, an ECL circuit E4, directly connected to the ECL circuit E3, and the surroundings of them are contained.
The ECL circuit E3 is comprised of NPN transistors Q31 and Q32, and a resistor Ro which pulls up collectors of the transistors Q31 and Q32 to a constant voltage Vr.
The ECL circuit E4 is similarly comprised of transistors Q41 and Q42, and the resistor Ro.
FIG. 10 is a wave form diagram showing the operations of the ECL circuits E3 and E4 shown in FIG. 9. When a voltage Vr-.DELTA.V is applied to an input 1 in the ECL circuit E3 while a voltage Vr is applied to an input 2 of it, voltage at Points a and b become Vr and Vr-.DELTA.V, respectively. In this case, however, there is the relations expressed in the above formula (1), and so, obtained is: EQU .DELTA.V=Ro.times.IO (2)
Voltage of the outputs 1 and 2 are Vr and Vr-.DELTA.V, respectively.
Similarly, when the voltage Vr and Vr-.DELTA.V are applied to the inputs I and 2, respectively, voltage Vr-.DELTA.V and Vr are generated at the outputs 1 and 2, respectively.
Assume now that the transistor Q32 has some fault, and so, the constant current I1 flows between the collector of the transistor Q32 and the ground GND indifferent to the voltage at the input 2. The voltage of the collector of the transistor Q32 is fixed in Vr-.DELTA.Vf. At this time, however, there is the following relation: EQU .DELTA.Vf=Ro.times.Il (3)
If now the relation .DELTA.Vf&gt;.DELTA.V is established, the potential of the base of the transistor Q41 (voltage at Point b) becomes always lower than the voltage of the base of the transistor Q42 (voltage at Point a), voltage at the outputs 1 and 2 cannot be controlled by variations in voltage at the inputs 1 and 2, and this fault can be detected.
As shown in FIG. 11, however, if the relation .DELTA.Vf &lt;.DELTA.V is established, the high - low level relation between the voltage at Point a and Point b is reversed in accordance with the variation of the voltage at the inputs 1 and 2, the resultant voltage of the outputs 1 and 2 become identical to the case shown in FIG. 10, and thus, the normal operation can be observed. In other words, no fault can be detected as to the transistor Q32.
Herein the resistor Ro has positive temperature characteristics, and the current IO generated by the constant current circuit 4 is controlled so as to cancel the characteristics. Therefore, .DELTA.V has a small dependence upon temperature. Meanwhile .DELTA.Vf has a large dependence upon temperature because the current I1 is not controlled unlike the current IO, and sometimes .DELTA.Vf and .DELTA.V vary in their relative levels if the temperature in testing an ECL circuit is different from the temperature in using it. Thus, sometimes a malfunction during the operation of the transistor Q32 cannot be detected
There are various ways of detecting the malfunction through a test: For example, the Voltage Vr at which the transistors Q31, Q32 are pulled up may be varied. However, the voltage Vr determined by the constant voltage circuit 3 inside the IC 100 cannot be easily varied for the test by the external operation outside the IC 100, so the detection of a fault of the transistor Q32 is impossible. Another way is detecting a fault of the transistor Q32 by varying a temperature in testing the ECL circuit, but accurate temperature control is needed during the test.
To sum up, a conventional semiconductor integrated circuit with an ECL circuit has the disadvantage that when some fault of the ECL circuit is externally detected, test stability and efficiency are not good.